Closed Branch

If you have marked a box or multiple contacts and execute the Insert Contact Parallel command, then a parallel branch is inserted with a single vertical line. For this kind of branching, the signal flow passes through both branches. This is an OR construct of both branches.

New: When you select a box and execute the Insert Contact Parallel command, a parallel branch is inserted with a single vertical line. This indicates that a short-circuit evaluation ("SCE") is implemented. SCE allows for the execution of a function block with a Boolean output to be bypassed when a specific condition is TRUE. The condition can be displayed in the LD editor as a branch connected parallel to the function block branch. The short circuit condition is defined by one or more contacts in this branch which are interconnected parallel or sequentially.

Functionality

The branches which do not include the function block are processed first. If CODESYS detects the value TRUE for one of these branch lines, then the function block is not called in the parallel branch. In this case, the value at the input of the function block is sent directly to the output. If CODESYS determines FALSE for the SCE condition, then the box is called and the Boolean result of its processing is passed on. If all branches contain function blocks, then they are analyzed from top to bottom and their outputs are logically ORed. If there are no branches with function blocks, then normal OR operations are performed.

Example 8. Example

The function block instance x1 (TON) has a Boolean input and a Boolean output. The execution of x1 is skipped if TRUE is determined for the condition in the parallel branch. The condition value results from the OR and AND operations which connect the contacts cond1, cond2, and cond3.

x1 is executed if the condition value from the connection of the contacts cond1, cond2, and cond3 is FALSE.

(1) Indicates from the double vertical connections that it is a construct subject to an SCE.

(2) Indicates from the single vertical connections that it is an OR construct.

The given LD example is displayed below as ST code. P_IN and P_OUT are the Boolean values at the input (split point) and output (reunification point) of the parallel branch.

P_IN := b1 AND b2;

IF ((P_IN AND cond1) AND (cond2 OR cond3)) THEN
   P_OUT := P_IN;
ELSE
   x1(IN := P_IN, PT := {p 10}t#2s);
   tElapsed := x1.ET;
   P_OUT := x1.Q;
END_IF
bRes := P_OUT AND b3;

For switching between an OR construct and an SCE, see also: Toggle Parallel Mode